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library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package UART_Components is
 
    function I2SLV(val,width : integer) return std_logic_vector;
    function SLV2I(val : std_logic_vector) return integer;
     
    component GenReg
        generic(Width : integer := 8);
        port(
            AClr    : in std_logic;
            Ck      : in std_logic;
            WEn     : in std_logic;
            OEn     : in std_logic;
            ShEn    : in std_logic;
            Cnt     : in std_logic;
            SIn     : in std_logic;
            D       : in std_logic_vector((Width-1) downto 0);
            Q       : out std_logic_vector((Width-1) downto 0);
            SOut    : out std_logic
            );
    end component;
 
    component BitPipe is
        generic(Length : integer := 2);
        port(
            Pr      : in std_logic;
            Clr     : in std_logic;
            Ck      : in std_logic;
            D       : in std_logic;
            Q       : out std_logic
            );
    end component;
 
    component TriSt is
        generic(Width : integer := 8);
        port(
            En      : in std_logic;
            Dir     : in std_logic;
            ChanA   : inout std_logic_vector((Width-1) downto 0);
            ChanB   : inout std_logic_vector((Width-1) downto 0)
            );
    end component;
 
    component Const is
        generic(
               Width    : integer := 8;
               Value    : integer := 0
               );
        port(
            Result  : out std_logic_vector((Width-1) downto 0)
            );
    end component;
 
    component Div2 is
        generic(Width : integer := 8);
        port(
            Operand : in std_logic_vector((Width-1) downto 0);
            Result  : out std_logic_vector((Width-1) downto 0)
            );
    end component;
 
    component GEQ is
        generic(Width : integer := 8);
        port(
            ChanA   : in std_logic_vector((Width-1) downto 0);
            ChanB   : in std_logic_vector((Width-1) downto 0);
            Result  : out std_logic
            );
    end component;
 
    component GT is
        generic(Width : integer := 8);
        port(
            ChanA   : in std_logic_vector((Width-1) downto 0);
            ChanB   : in std_logic_vector((Width-1) downto 0);
            Result  : out std_logic
            );
    end component;
 
    component EQ is
        generic(Width : integer := 8);
        port(
            ChanA   : in std_logic_vector((Width-1) downto 0);
            ChanB   : in std_logic_vector((Width-1) downto 0);
            Result  : out std_logic
            );
    end component;
 
    component Mux2 is
        port(
            Sel     : in std_logic;
            ChanA   : in std_logic;
            ChanB   : in std_logic;
            Result  : out std_logic
            );
    end component;
 
    component Mux4 is
        port(
            Sel     : in std_logic_vector(1 downto 0);
            ChanA   : in std_logic;
            ChanB   : in std_logic;
            ChanC   : in std_logic;
            ChanD   : in std_logic;
            Result  : out std_logic
            );
    end component;
 
    component BusMux2 is
        generic(Width : integer := 8);
        port(
            Sel     : in std_logic;
            ChanA   : in std_logic_vector((Width-1) downto 0);
            ChanB   : in std_logic_vector((Width-1) downto 0);
            Result  : out std_logic_vector((Width-1) downto 0)
            );
    end component;
 
    component BusMux4 is
        generic(Width : integer := 8);
        port(
            Sel     : in std_logic_vector(1 downto 0);
            ChanA   : in std_logic_vector((Width-1) downto 0);
            ChanB   : in std_logic_vector((Width-1) downto 0);
            ChanC   : in std_logic_vector((Width-1) downto 0);
            ChanD   : in std_logic_vector((Width-1) downto 0);
            Result  : out std_logic_vector((Width-1) downto 0)
            );
    end component;
 
    component DeMux2 is
        port(
            Sel     : in std_logic;
            Source  : in std_logic;
            ChanA   : out std_logic;
            ChanB   : out std_logic
            );
    end component;
 
    component DeMux4 is
        port(
            Sel     : in std_logic;
            Source  : in std_logic;
            ChanA   : out std_logic;
            ChanB   : out std_logic;
            ChanC   : out std_logic;
            ChanD   : out std_logic
            );
    end component;
 
    component BusDeMux2 is
        generic(Width : integer := 8);
        port(
            Sel     : in std_logic;
            Source  : in std_logic_vector((Width-1) downto 0);
            ChanA   : out std_logic_vector((Width-1) downto 0);
            ChanB   : out std_logic_vector((Width-1) downto 0)
            );
    end component;
 
    component BusDeMux4 is
        generic(Width : integer := 8);
        port(
            Sel     : in std_logic;
            Source  : in std_logic_vector((Width-1) downto 0);
            ChanA   : out std_logic_vector((Width-1) downto 0);
            ChanB   : out std_logic_vector((Width-1) downto 0);
            ChanC   : out std_logic_vector((Width-1) downto 0);
            ChanD   : out std_logic_vector((Width-1) downto 0)
            );
    end component;
     
end package;
 
package body UART_Components is
 
    function I2SLV(Val,Width : integer) return std_logic_vector is
    variable Result : std_logic_vector((Width-1) downto 0) := (others => '0');
    variable Bits : integer := Width;
    begin
 
        if(Bits > 32)then
         Bits := 32;
        end if;
 
        assert 2** Bits > Val report
        "Value too big for std_logic_vector width"
        severity Warning;
 
        for i in 0 to (Bits-1) loop
 
            if((Val/(2**i)) mod 2 = 1)then
 
                Result(i) := '1';
 
            end if;
 
        end loop;
 
        return Result;
 
    end function;
 
    function SLV2I(val : std_logic_vector) return integer is
    variable result : integer := 0;
    variable count : integer := 0;
    begin
 
        bits : for i in val'low to val'high loop
 
            if(val(val'high - i) = '1')then
 
                result := result + (2**(i - val'low));
 
            end if;
 
            count := count + 1;
 
            exit bits when count = 32;
 
        end loop bits;
 
        return result;
 
    end function;
 
end package body;
 
-- A general purpose scalable clocked register which implements;
--
 Asynchronous clear
-- Asynchronous output enable
-- Synchronous write enable
-- Synchronous right shift enable
-- Synchronous incrementing count enable
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
 
entity GenReg is
    generic(Width : integer := 8);
    port(
        AClr    : in std_logic;
        Ck      : in std_logic;
        WEn     : in std_logic;
        OEn     : in std_logic;
        ShEn    : in std_logic;
        Cnt     : in std_logic;
        SIn     : in std_logic;
        D       : in std_logic_vector((Width-1) downto 0);
        Q       : out std_logic_vector((Width-1) downto 0);
        SOut    : out std_logic
        );
end entity;
 
architecture GenReg_A1 of GenReg is  
 
signal Buf : unsigned((Width-1) downto 0);
 
begin
 
    process(AClr,Ck)
    begin
         
        if(AClr = '0')then
             
            Buf <= (others => '0');
             
        elsif rising_edge(Ck) then
 
            if(WEn = '1')then
 
                Buf <= UNSIGNED(D);
 
            elsif(Cnt = '1') then
 
                Buf <= Buf + 1;
 
            elsif(ShEn = '1') then
 
                Buf <= Buf srl 1;
                Buf(Width-1) <= SIn;
 
            end if;
             
        end if;
         
    end process;
 
    SOut <= Buf(0);
 
    -- Tristate outputs controlled by OEn
    process(OEn,Buf)
    begin
 
        if(OEn = '1')then
 
            Q <= std_logic_vector(Buf);
 
        else
 
            Q <= (others => 'Z');
 
        end if;
 
    end process;
     
end architecture;
 
-- A variable length synchronous bit pipe
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity BitPipe is
    generic(Length : integer := 2);
    port(
        Pr      : in std_logic;
        Clr     : in std_logic;
        Ck      : in std_logic;
        D       : in std_logic;
        Q       : out std_logic
        );
end entity;
 
architecture BitPipe_A1 of BitPipe is    
signal Pipe     : std_logic_vector((Length-1) downto 0);
begin
 
    process(Pr,Clr,Ck)
    begin
 
        if(Pr = '0')then
 
            Pipe <= (others => '1');
 
        elsif(Clr = '0')then
 
            Pipe <= (others => '0');
 
        elsif(rising_edge(Ck))then
 
            Pipe(Length-1) <= D;
 
            for i in (Length-2) downto 0 loop
 
                Pipe(i) <= Pipe(i+1);
 
            end loop;
 
        end if;
 
    end process;
 
    Q <= Pipe(0);
 
end architecture;
 
-- An asynchronous scalable bidirectional tristate buffer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity TriSt is
    generic(Width : integer := 8);
    port(
        En      : in std_logic;
        Dir     : in std_logic;
        ChanA   : inout std_logic_vector((Width-1) downto 0);
        ChanB   : inout std_logic_vector((Width-1) downto 0)
        );
end entity;
 
architecture TriSt_A1 of TriSt is    
begin
 
    process(En,Dir,ChanA,ChanB)
    begin
 
        if(En = '1')then
 
            if(Dir = '0')then
 
                ChanB <= ChanA;
 
            else
 
                ChanA <= ChanB;
 
            end if;
 
        else
 
            ChanA <= (others => 'Z');
            ChanB <= (others => 'Z');
 
        end if;
 
    end process;
 
end architecture;
 
-- A generic constant value
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.UART_Components.all;
 
entity Const is
    generic(
           Width    : integer := 8;
           Value    : integer := 0
           );
    port(
        Result  : out std_logic_vector((Width-1) downto 0)
        );
end entity;
 
architecture Const_A1 of Const is    
constant Cnst : std_logic_vector((Width-1) downto 0) := I2SLV(Value,Width);
begin
 
    Result <= Cnst;
 
end architecture;
 
 
-- An asynchronous division by two
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity Div2 is
    generic(Width : integer := 8);
    port(
        Operand : in std_logic_vector((Width-1) downto 0);
        Result  : out std_logic_vector((Width-1) downto 0)
        );
end entity;
 
architecture DIV2_A1 of Div2 is  
begin
 
    process(Operand)
    begin
 
        Result(Width-1) <= '0';
 
        for i in (Width-2) downto 0 loop
 
            Result(i) <= Operand(i+1);
 
        end loop;
 
    end process;
 
end architecture;
 
-- An asynchronous scalable comparator
 GEQ
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity GEQ is
    generic(Width : integer := 8);
    port(
        ChanA   : in std_logic_vector((Width-1) downto 0);
        ChanB   : in std_logic_vector((Width-1) downto 0);
        Result  : out std_logic
        );
end entity;
 
architecture GEQ_A1 of GEQ is    
begin
 
    process(ChanA,ChanB)
    begin
 
        if(ChanA >= ChanB)then
 
            Result <= '1';
 
        else
 
            Result <= '0';
 
        end if;
 
    end process;
 
end architecture;
 
-- An asynchronous scalable comparator GT
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity GT is
    generic(Width : integer := 8);
    port(
        ChanA   : in std_logic_vector((Width-1) downto 0);
        ChanB   : in std_logic_vector((Width-1) downto 0);
        Result  : out std_logic
        );
end entity;
 
architecture GT_A1 of GT is  
begin
 
    process(ChanA,ChanB)
    begin
 
        if(ChanA > ChanB)then
 
            Result <= '1';
 
        else
 
            Result <= '0';
 
        end if;
 
    end process;
 
end architecture;
 
-- An asynchronous scalable comparator EQ
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity EQ is
    generic(Width : integer := 8);
    port(
        ChanA   : in std_logic_vector((Width-1) downto 0);
        ChanB   : in std_logic_vector((Width-1) downto 0);
        Result  : out std_logic
        );
end entity;
 
architecture EQ_A1 of EQ is  
begin
 
    process(ChanA,ChanB)
    begin
 
        if(ChanA = ChanB)then
 
            Result <= '1';
 
        else
 
            Result <= '0';
 
        end if;
 
    end process;
 
end architecture;
 
-- A scalable fully asynchronous two port multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity Mux2 is
    port(
        Sel     : in std_logic;
        ChanA   : in std_logic;
        ChanB   : in std_logic;
        Result  : out std_logic
        );
end entity;
 
architecture Mux2_A1 of Mux2 is  
begin
 
    process(Sel,ChanA,ChanB)
    begin
 
        case(Sel)is
 
            when '0' =>
 
                Result <= ChanA;
 
            when '1' =>
 
                Result <= ChanB;
 
            when others =>
 
                Result <= '0';
 
        end case;
 
    end process;
 
end architecture;
 
-- A scalable fully asynchronous four port multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity Mux4 is
    port(
        Sel     : in std_logic_vector(1 downto 0);
        ChanA   : in std_logic;
        ChanB   : in std_logic;
        ChanC   : in std_logic;
        ChanD   : in std_logic;
        Result  : out std_logic
        );
end entity;
 
architecture Mux4_A1 of Mux4 is
begin
 
    process(Sel,ChanA,ChanB,ChanC,ChanD)
    begin
 
        case(Sel)is
 
            when "00" =>
 
                Result <= ChanA;
 
            when "01" =>
 
                Result <= ChanB;
 
            when "10" =>
 
                Result <= ChanC;
 
            when "11" =>
 
                Result <= ChanD;
 
            when others =>
 
                Result <= '0';
 
        end case;
 
    end process;
 
end architecture;
 
-- A scalable fully asynchronous two port bus multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity BusMux2 is
    generic(Width : integer := 8);
    port(
        Sel     : in std_logic;
        ChanA   : in std_logic_vector((Width-1) downto 0);
        ChanB   : in std_logic_vector((Width-1) downto 0);
        Result  : out std_logic_vector((Width-1) downto 0)
        );
end entity;
 
architecture BusMux2_A1 of BusMux2 is    
begin
 
    process(Sel,ChanA,ChanB)
    begin
 
        case(Sel)is
 
            when '0' =>
 
                Result <= ChanA;
 
            when '1' =>
 
                Result <= ChanB;
 
            when others =>
 
                Result <= (others => '0');
 
        end case;
 
    end process;
 
end architecture;
 
-- A scalable fully asynchronous four port bus multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity BusMux4 is
    generic(Width : integer := 8);
    port(
        Sel     : in std_logic_vector(1 downto 0);
        ChanA   : in std_logic_vector((Width-1) downto 0);
        ChanB   : in std_logic_vector((Width-1) downto 0);
        ChanC   : in std_logic_vector((Width-1) downto 0);
        ChanD   : in std_logic_vector((Width-1) downto 0);
        Result  : out std_logic_vector((Width-1) downto 0)
        );
end entity;
 
architecture BusMux4_A1 of BusMux4 is
begin
 
    process(Sel,ChanA,ChanB,ChanC,ChanD)
    begin
 
        case(Sel)is
 
            when "00" =>
 
                Result <= ChanA;
 
            when "01" =>
 
                Result <= ChanB;
 
            when "10" =>
 
                Result <= ChanC;
 
            when "11" =>
 
                Result <= ChanD;
 
            when others =>
 
                Result <= (others => '0');
 
        end case;
 
    end process;
 
end architecture;
 
-- A scalable fully asynchronous two port demultiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity DeMux2 is
    port(
        Sel     : in std_logic;
        Source  : in std_logic;
        ChanA   : out std_logic;
        ChanB   : out std_logic
        );
end entity;
 
architecture DeMux2_A1 of DeMux2 is  
begin
 
    process(Sel,Source)
    begin
 
        case(Sel)is
 
            when '0' =>
 
                ChanA <= Source;
                ChanB <= '0';
 
            when '1' =>
 
                ChanA <= '0';
                ChanB <= Source;
 
            when others =>
 
                ChanA <=  '0';
                ChanB <=  '0';
 
        end case;
 
    end process;
 
end architecture;
 
-- A scalable fully asynchronous four port demultiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity DeMux4 is
    port(
        Sel     : in std_logic_vector(1 downto 0);
        Source  : in std_logic;
        ChanA   : out std_logic;
        ChanB   : out std_logic;
        ChanC   : out std_logic;
        ChanD   : out std_logic
        );
end entity;
 
architecture DeMux4_A1 of DeMux4 is  
begin
 
    process(Sel,Source)
    begin
 
        case(Sel)is
 
            when "00" =>
 
                ChanA <= Source;
                ChanB <= '0';
                ChanC <= '0';
                ChanD <= '0';
 
            when "01" =>
 
                ChanA <= '0';
                ChanB <= Source;
                ChanC <= '0';
                ChanD <= '0';
 
            when "10" =>
 
                ChanA <= '0';
                ChanB <= '0';
                ChanC <= Source;
                ChanD <= '0';
 
            when "11" =>
 
                ChanA <= '0';
                ChanB <= '0';
                ChanC <= '0';
                ChanD <= Source;
 
 
            when others =>
 
                ChanA <= '0';
                ChanB <= '0';
                ChanC <= '0';
                ChanD <= '0';
 
        end case;
 
    end process;
 
end architecture;
 
-- A scalable fully asynchronous two port bus demultiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity BusDeMux2 is
    generic(Width : integer := 8);
    port(
        Sel     : in std_logic;
        Source  : in std_logic_vector((Width-1) downto 0);
        ChanA   : out std_logic_vector((Width-1) downto 0);
        ChanB   : out std_logic_vector((Width-1) downto 0)
        );
end entity;
 
architecture BusDeMux2_A1 of BusDeMux2 is    
begin
 
    process(Sel,Source)
    begin
 
        case(Sel)is
 
            when '0' =>
 
                ChanA <= Source;
                ChanB <= (others => '0');
 
            when '1' =>
 
                ChanA <= (others => '0');
                ChanB <= Source;
 
            when others =>
 
                ChanA <= (others => '0');
                ChanB <= (others => '0');
 
        end case;
 
    end process;
 
end architecture;
 
-- A scalable fully asynchronous four port bus demultiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity BusDeMux4 is
    generic(Width : integer := 8);
    port(
        Sel     : in std_logic_vector(1 downto 0);
        Source  : in std_logic_vector((Width-1) downto 0);
        ChanA   : out std_logic_vector((Width-1) downto 0);
        ChanB   : out std_logic_vector((Width-1) downto 0);
        ChanC   : out std_logic_vector((Width-1) downto 0);
        ChanD   : out std_logic_vector((Width-1) downto 0)
        );
end entity;
 
architecture BusDeMux4_A1 of BusDeMux4 is    
begin
 
    process(Sel,Source)
    begin
 
        case(Sel)is
 
            when "00" =>
 
                ChanA <= Source;
                ChanB <= (others => '0');
                ChanC <= (others => '0');
                ChanD <= (others => '0');
 
            when "01" =>
 
                ChanA <= (others => '0');
                ChanB <= Source;
                ChanC <= (others => '0');
                ChanD <= (others => '0');
 
            when "10" =>
 
                ChanA <= (others => '0');
                ChanB <= (others => '0');
                ChanC <= Source;
                ChanD <= (others => '0');
 
            when "11" =>
 
                ChanA <= (others => '0');
                ChanB <= (others => '0');
                ChanC <= (others => '0');
                ChanD <= Source;
 
 
            when others =>
 
                ChanA <= (others => '0');
                ChanB <= (others => '0');
                ChanC <= (others => '0');
                ChanD <= (others => '0');
 
        end case;
 
    end process;
 
end architecture;
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Last modified: SolFlu Mon, 19 Oct 2009 17:58:08 GMT